Embodiments of the present invention relate to logic gates. In particular, embodiments of the present invention relate to the topology of differential domino logic gates.
Domino logic is often used in high speed integrated circuits. A domino circuit is a type of circuit that is arranged in stages with the outputs from one stage used as inputs into the next stage. A stage in the domino circuit may be, for example, a logic gate. The clock used with a domino circuit typically is delayed for each of the individual stages to provide a set-up time for the stages. The individual domino logic gates typically have one or more precharge blocks, which force the circuit to a known state during one phase of a clock, and one or more evaluation blocks, which provide output values that are based on the input values. In such domino circuits, the clock may be said to have a precharge phase and an evaluation phase.
Domino circuits generally have a static stage in between the domino stages. For example, the domino circuit may have an inverter between the domino stages or a static complimentary metal-oxide semiconductor (CMOS) gate between the domino stages. Another example is the zipper domino circuit, which has a P-channel metal-oxide semiconductor (PMOS) gate between the domino stages. In a cascaded domino circuit, the outputs from one N-channel metal-oxide semiconductor (NMOS) domino gate (i.e., a gate with NMOS transistors in the evaluation block) may be directly connected to the inputs of another NMOS domino gate. Thus, a cascaded domino circuit does not have any invertors, static stages, or PMOS gates in the critical path of the logic.
Domino logic gates may be constructed as differential circuits. A differential circuit has complimentary sets of input and output terminals. The first set of input and output terminals may be referred to as the xe2x80x9ctruexe2x80x9d inputs and outputs, and the second set may be referred to as the xe2x80x9ccomplimentxe2x80x9d inputs and outputs. For example, a differential xe2x80x9cAND gatexe2x80x9d may have a set of true inputs and may have a true output that outputs the result of a logical AND function for the true inputs. In addition, the differential AND gate may have a set of compliment inputs, each of which may receive the compliment values of that received by the corresponding true input, and may have a compliment output that outputs the compliment value of the true output.
Differential domino circuits have been shown to operate at higher speeds and have a smaller size that other comparable circuits. Some differential domino circuits, such as the cascaded differential domino circuits, may be difficult to design and manufacture because the true and compliment outputs of the gates in the circuit should begin to switch with the same edge rate and not be susceptible to pattern dependence. In addition, the clock may arrive at the same time, or before, the data. For these reasons, differential domino circuits such as cascaded differential domino circuits have not been widely used.